1. Field of the Invention
The present invention relates to a method of etching a semiconductor substrate and more specifically to a method of stably etching a semiconductor substrate without being subjected to the influence of fluctuations in various etching conditions.
2. Description of the Prior Art
FIG. 1 shows an example of prior-art electrolytic etching apparatus, which comprises an electrolytic bath 1, an etching liquid (electrolytic solution) 2 put in the electrolytic bath 1, a semiconductor substrate 3 such as a silicon substrate, an electrode 4 opposing to the substrate 3, a reference electrode 6 made of silver and/or silver chloride Ag/AgCl, and a variable voltage power supply 5 including a potentiostat. A dc voltage V1 applied between the opposing electrode 4 and the semiconductor substrate 3 is controlled by the variable voltage power supply 5, so that a potential V2 of the semiconductor substrate 3 relative to the reference electrode 6 can be maintained at a predetermined value.
A method of etching a semiconductor substrate 3 as shown in FIG. 2A will be explained by way of example. In the semiconductor substrate 3 shown in FIG. 2A, an n-type epitaxial layer 3b is formed on a p-type substrate 3a; a p-type diffusion layer 3c is formed in this n-type epitaxial layer 3b; and two opposite silicon oxide films 3d and 3e are patterned on the n-type epitaxial layer 3b and the p-type substrate 3a, respectively. Further, an aluminium electrode 3f is formed on the n-type epitaxial layer 3b and the silicon oxide film 3d.
The p-type substrate 3a of the semiconductor substrate 3 as shown 2A can be electrolytically etched with the electrolytic etching apparatus as shown in FIG. 1 in accordance with etching characteristics as shown in FIG. 3A.
FIG. 3A shows the relationship between the electrode potential V2 (V) of the substrate 3 relative to the reference electrode 6 (Ag/AgCl) and the current density (mA/cm.sup.2) flowing through the substrate 3, the etching rate (.mu.m/min), in which a solid line N1, denotes the current density of n-type silicon substrate; a solid line P1 denotes that of p-type silicon substrate; a dashed line N2 denotes the etching rate of n-type silicon substrate; and P2 denotes that of p-type silicon substrate.
FIG. 3A indicates that the current density increases with increasing substrate potential relative to the reference electrode (Ag/AgCl) 6 but drops sharply at a substrate potential of about -0.95 V or higher in the case of n-type silicon substrate and of about -0.75 V or higher in the case of p-type silicon substrate. This is because as the substrate potential relative to the reference electrode 6 increases, oxide current is generated so that an anodic oxidation film is inevitably formed on the surface of the substrate 3. Here, the potential at which the current density starts to drop sharply is referred to as passivation potential. As shown in FIG. 3A, the passivation potential of n-type silicon layer (-0.95 V) is lower by about 0.2 V than that (-0.75 V) of p-type silicon layer. Therefore, when the potential of the semiconductor substrate 3 relative to the reference electrode 6 is kept at Vb=-0.8 V, for instance, it is possible to obtain such a potential condition that n-type silicon will not be etched but p-type silicon can be etched, as shown by the dashed lines N2 and P2 in FIG. 3A.
Accordingly, when the semiconductor substrate 3 is electrolytically etched by maintaining the substrate potential V2 relative to the reference electrode 6 under these condition by controlling the variable voltage power supply 5 while monitoring the current density flowing through the substrate 3, it is possible to selectively etch the p-type substrate 3a and the p-type diffusion layer 3c of the semiconductor substrate, without etching the n-type layer 3b, with the patterned silicon oxide film 3e as mask, until the p-type diffusion layer 3c is etched to the silicon oxide film 3d, as depicted in FIG. 2B.
In this connection, when a voltage is being applied, since the pn junction is formed between the p-type silicon substrate 3a and the n-type silicon layer 3b under backward reversed bias condition (since a position voltage is applied to the n-type layer 3b), no voltage is applied to the p-type silicon layer 3c at the start of etching. However, when the p-type silicon substrate 3a is etched in such a degree that the n-type silicon layer 3b is exposed, since a voltage is applied to an interface between the n-type silicon layer 3b and the etching liquid, the p-type layer 3c can be etched. However, when the voltage applied to the interface rises up to 3.6 V or higher, since an anodic oxidation film is formed on the surface of the n-type silicon layer 3b, no current flows, as is well known. In other words, the n-type silicon layer 3b will not be etched, because the formed anodic oxidation film serves as a mask. Therefore, it is possible to selectively etch only the p-type silicon substrate 3 a by keeping the applied voltage at 3.6 V or higher.
However, when a high voltage of 3.6 V or higher is kept applied from the initial etching stage, there exists such a problem as described below.
For instance, in the case where the etching liquid is 100% hydrazine hydrate heated at 95.degree. C. and the masking material is 1 .mu.m-thick PSG (phospho-silicate Glass) film or 1 .mu.m-thick silicon nitride film formed by plasma CVD (Chemical Vapor Deposition), if the semiconductor substrate 3 is etched by keeping the potential of the substrate 3 relative to the reference electrode 6 at -0.8 V, there exists a problem, as shown in FIG. 3B, in that the mask material is locally damaged and therefore the surface of the silicon substrate 3 is partially exposed under the mask at time t1 (e.g. after 2 hours), so that the p-type silicon substrate 3a under the mask is inevitably etched. Accordingly, current increases sharply after t1, and further continues to increase after etching has reached the interface between the p-type substrate 3a and the n-type layer 3b. In summary, when a relatively high voltage is applied from the start of etching, there exists a problem in that the mask material is also etched, so that the production yield of the semiconductor substrate is markedly reduced.